Beside the Cycle: Cadence Design Systems

The secular shift underway in artificial intelligence is undeniable. AI, autonomous vehicles, and advanced cloud infrastructure are driving a structural surge in semiconductor content across every layer of the global economy. Not investing in the sector that is enabling this transformation risks missing a defining growth theme of the coming decade. Yet most of the semiconductor industry sits outside our investment universe. This is not due to a failure to appreciate its technological importance, but a considered judgement that it falls short of the strict criteria that define our quality growth philosophy.

Traditional semiconductor companies fail to meet many of our Golden Rules but most significantly, the problem is capital intensity and the cyclicality it creates. These are businesses whose earnings are structurally unpredictable, which makes them incompatible with how we think about compounding long-term returns. In the Electronic Design Automation industry, we believe we have found a business which gives us exposure to the AI-driven growth in semiconductor demand, while still exhibiting the predictable, high-quality economics our philosophy was built to identify – Cadence Design Systems.¹

Cadence: A leader in EDA

Cadence is a global leader in the Electronic Design Automation (EDA) industry, with over 30 years of computational software expertise. It provides the critical software tools and intellectual property required to design modern semiconductor chips and complex electronic devices. To understand what Cadence does, it helps to think about the scale of the problem it solves. A modern AI chip (AI accelerator) or high-end smartphone processor contains between 50 and 200 billion transistors. Every single one must be precisely specified, placed, routed, and verified before any physical chip is manufactured. This process typically involves thousands of engineers working across different functional blocks, using highly specialised software (EDA) tools to translate architectural intent into manufacturable silicon geometry, and takes anywhere from eighteen months to three years, before moving onto the manufacturing process.

The competitive landscape in EDA is a duopoly. Cadence and Synopsys together command approximately 80–85 per cent of the global EDA market, with Mentor Graphics (now part of Siemens EDA) holding most of the remainder. The barriers to entry are high: EDA tools require decades of algorithmic development, deep integration into customer workflows, and continuous co-development with foundries such as TSMC to remain certified for each new process node. Switching costs are among the highest in enterprise software. As an industry expert put it: replacing the tools mid-project is operationally equivalent to switching accounting systems during an audit, theoretically possible, practically catastrophic.

Cadence’s deep technical expertise and entrenched competitive advantage translate directly into a financial profile characterized by the high quality of its revenue and superior profitability. Approximately 80–90 per cent of its revenue is recurring, recognised ratably over multi-year contracts. The compound annual revenue growth rate was over 14 per cent for the last 5 years and approximately 12 per cent over the last decade. In 2025, Cadence reported $5.3 billion in revenue and entered 2026 with an $8 billion backlog of contractually committed future revenue. Simultaneously Cadence steadily expanded its non-GAAP operating margin into the 42–45 per cent range. With a capex-to-sales ratio of just 2-3 per cent, the business generates exceptional return on invested capital (excluding goodwill), averaging above 70 per cent,² making it one of the highest quality businesses in the Seilern Universe.

Why Cadence sidesteps the semiconductor cycle

The stability of Cadence’s earnings contrasts sharply with the wider semiconductor industry whose chips it helps design. Cadence retains this predictability for three key reasons.

First, it is much less capital intensive. Traditional semiconductor companies are capital-intensive by their nature. A single leading-edge fabrication plant costs $15–20 billion to construct, takes three to five years to bring online and cannot easily be repurposed once built. This multi-year gap between investment and production creates a fundamental supply-demand mismatch: by the time new capacity comes online, market conditions often have shifted. If demand softens, foundries suffer severe margin compression, as they must absorb relentless fixed-asset depreciation against a much smaller revenue base.

Cadence faces none of this. Its core product is software, with near-zero marginal cost to produce and deliver. When demand softens there is no stranded capacity, no half-utilised factory depreciating on the balance sheet. Its primary investment goes into Research & Development (R&D), such as adapting tools to new process nodes, new design paradigms and AI integration. Unlike physical assets which depreciate from the moment they are commissioned, R&D often produces compounding intellectual property that strengthens its competitive position with every cycle.

The second reason is Cadence’s insulation from the “bullwhip effect”. The bullwhip effect happens in a multi-tiered supply chain, when small, localized fluctuations in end demand produce progressively larger order distortions as signals travel upstream. This is because each node in the chain adds safety stock or draws it down, compounding forecasting errors. In semiconductors, this effect is particularly strong: a modest 5 per cent contraction in smartphone or PC demand can translate into a 50 per cent collapse at the silicon manufacturing level as the entire chain simultaneously flushes out excess inventory.

Because Cadence doesn’t produce any physical goods that flow through the semiconductor supply chain, it is virtually immune to this volatility – a chip designer does not buy more EDA licences to meet a surge in production demand, nor can they hold excess software inventory as safety stock. To put it simply, Cadence does not sit “within” the supply chain, but “beside” it. Its revenue, hence, is not tied to how many chips are manufactured, but to how many engineers are doing design work and how complex their designs are.

This brings us to the third reason: Cadence’s revenues are primarily driven by semiconductor R&D expenditure, and R&D is often the last budget line to be cut in a downturn because it directly drives a company’s future competitiveness. When semi production hits its cyclical trough, management often double down on design activities, developing the next-generation chip to compete their way out of the bottom and capture market share in the next upcycle. In other words, the semiconductor cycle is a production cycle, whereas Cadence’s business runs on a design cycle. The two differ fundamentally in amplitude and timing: where production is wildly volatile, design has secular stability, a defensive buffer even when chip production collapses.

The post-pandemic downturn illustrates this clearly. Intel’s revenue declined 20 per cent in full-year 2022 and a further 36 per cent year-on-year in Q1 2023. Its EDA spending did not follow (as seen in strong revenue growth by EDA vendors in the same period shown in the graph below). Intel could not reduce its core engineering headcount by a third without forfeiting its product roadmap, so those engineers stayed, the design mandate grew more urgent, and EDA vendors like Cadence continued collecting licensing fees.

Figure 1: Comparison of Intel and EDA Vendor Revenue Growth 2018 – 2025

Conclusion

Despite all these merits, Cadence is not immune to the semiconductor cycle. During severe recessions, R&D budgets could eventually compress, and design activity slows. Cadence also operates a hardware segment, its Palladium and Protium emulation and prototyping systems,³ which although not tied to the semi production cycle, are still physical capital goods, and as such are more easily deferred and inherently lumpier in demand. With this segment now concentrated in hyperscaler AI chip design, any pause in AI capital would be felt relatively quickly. More broadly, the current environment is unusually elevated, charged by a massive AI capex cycle. Should the commercialization and software-level monetization of generative AI fail to yield sufficient returns for enterprises, hyperscalers may pull back their capital materially and a severe downcycle would follow. 

What Cadence offers is not immunity from risk, no investment does, but a fundamentally more favourable risk profile than the main semiconductor industry it serves. In an era of rising design complexity, driven by AI and the proliferation of custom silicon across industries, the demand for chip design activity has a secular growth trajectory that is structurally decoupled from the production cycle. Cadence therefore offers exposure to the structural expansion of the semiconductor era without the capital intensity, earnings volatility, or cyclical drawdowns that make traditional semiconductor manufacturers incompatible with our investment framework. It is, in our view, precisely the kind of durable, compounding business that our philosophy was built to identify and own.

¹ Seilern funds bought Cadence Design Systems in Jan 2025.

² Over the past five years.

³ Cadence does not break out revenue for this segment. So, we estimated it contributes roughly 8-10% of total group revenue.